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1200 days ago

Changelog History
Page 2

  • v0.99.1 Changes

    May 12, 2018
    • Allow ~NAME[N] tag inside ~GENSYM[X]
    • 👍 Support HDL record selector generation #313 <>__
    • 👍 InlinePrimitive support: specify HDL primitives inline with Haskell code
    • 👍 Support for ghc-typelits-natnormalise-0.6.1
    • Lift instances for TopEntity and PortName
    • 👍 InlinePrimitive support: specify HDL primitives inline with Haskell code
  • v0.99 Changes

    March 31, 2018
    • New features:
    • Major API overhaul: check the migration guide at the end of Clash.Tutorial
    • New features:

      • Explicit clock and reset arguments
      • Rename CLaSH to Clash
      • Implicit/\ Hidden clock and reset arguments using a combination of reflection and ImplicitParams.
      • Large overhaul of TopEntity annotations
      • PLL and other clock sources can now be instantiated using regular functions: Clash.Intel.ClockGen and Clash.Xilinx.ClockGen.
      • DDR registers:
      • Generic/ASIC: Clash.Explicit.DDR
      • Intel: Clash.Intel.DDR
      • Xilinx: Clash.Intel.Xilinx
    • Bit is now a newtype instead of a type synonym and will be mapped to a HDL scalar instead of an array of one (e.g std_logic instead of std_logic_vector(0 downto 0))

    • Hierarchies with multiple synthesisable boundaries by allowing more than one function in scope to have a Synthesize annotation.

      • Local caching of functions with a Synthesize annotation
    • Bit type is mapped to a HDL scalar type (e.g. std_logic in VHDL)

    • Improved name preservation

    • Zero-bit values are filtered out of the generated HDL

    • Improved compile-time computation

    • 🛠 Many bug fixes

    Older versions

    Check out: * * *

  • v0.7.2 Changes

    April 25, 2017
    • 🆕 New features:
      • Sum-of-product types: unused bits now "don't-care" #212
    • 🛠 Fixes bugs:
  • v0.7.1 Changes

    April 11, 2017
    • 🆕 New features:
      • Support distribution of primitive templates with Cabal/Hackage packages commit
      • Find memory data files and primitive files relative to import dirs (-i<DIR>)
      • Add 'clashi' program and 'clash-ghc' package #208, thanks to @thoughtpolice
    • 🛠 Fixes bugs:
      • case (EmptyCase ty) of ty' { ... } -> EmptyCase ty' #198
      • BitVector.split# apply the correct type arguments
      • SystemVerilog: Incorrect unsigned->signed wrap-around and conversion
      • SystemVerilog: Use unpacked array syntax in array literals
      • SystemVerilog: Add braces when converting unpacked to packed arrays
      • SystemVerilog: Fixed rotateLeftS systemverilog template
      • SystemVerilog: Do not generate null-slices
      • Verilog: Incorrect unsigned->signed wrap-around and conversion
      • VHDL: resize Integer multiplication result
  • v0.7 Changes

    January 16, 2017
    • 🆕 New features:
      • CLaSH.XException: a module defining an exception representing uninitialised values. Additionally adds the ShowX class which has methods that prints values as "X" where they would normally raise an XException exception.
      • Add BNat (and supporting functions) to CLaSH.Promoted.Nat: base-2 encoded natural numbers.
      • Add divSNat and logBaseSNat to CLaSH.Promoted.Nat: division and logarithm for singleton natural numbers.
      • Add predUNat and subUNat to CLaSH.Promoted.Nat: predecessor and subtraction for unary-encoded natural numbers.
      • Add dtfold to CLaSH.Sized.Vector: a dependently-typed tree-fold over Vec.
      • Add the perfect-depth binary trees module CLaSH.Sized.RTree
      • Synthesisable definitions of countLeadingZeros and countTrailingZeros for: BitVector, Signed, Unsigned, and Fixed
      • Add the (:::) type alias in CLaSH.NamedTypes which allows you to annotate types with documentation
    • 🔄 Changes:
      • asyncRam, blockRam, blockRamFile have a Maybe (addr,a) as write input instead of three separate Bool, addr, and a inputs.
      • asyncFIFOSynchronizer has a Maybe a as write-request instead of a separate Bool and a input
      • bundle' and unbundle' are removed; bundle now has type Unbundled' clk a -> Signal' clk a, unbundle now has type Signal' clk a -> Unbundled' clk a
      • subSNat now has the type SNat (a+b) -> SNat b -> SNat a (where it used to be SNat a -> SNat b -> SNat (a-b))
      • Renamed multUNat to mulUNat to be in sync with mulSNat and mulBNat.
      • The function argument of vfold in CLaSH.Sized.Vector is now (forall l . SNat l -> a -> Vec l b -> Vec (l + 1) b) (where it used to be (forall l . a -> Vec l b -> Vec (l + 1) b))
      • Cons constructor of Vec is no longer visible; (:>) and (:<) are now listed as constructors of Vec
      • Simulation speed improvements for numeric types
  • v0.6.24 Changes

    October 17, 2016
    • Call generatePrimMap after loadModules #175
    • 🛠 Fixes bugs:
      • (System)Verilog: CLaSH.Sized.Vector.imap primitive gets indices in reverse order
      • Template Haskell splices are run twice
      • CLaSH errors out when observing the constructor for Signal #174
  • v0.6.22 Changes

    August 03, 2016
    • 🛠 Fixes bugs:
      • Bug in DEC transformation overwrites case-alternatives
      • Bug in DEC transformation creates non-representable let-binders
      • VHDL: Incorrect primitive for Integers ltInteger# and geInteger#
      • (System)Verilog: Fix primitive for CLaSH.Sized.Internal.Signed.mod# and GHC.Type.Integer.modInteger #164
  • v0.6.20 Changes

    July 15, 2016
    • 🆕 New features:
      • Better error location reporting
    • 🛠 Fixes bugs:
      • CLaSH.Sized.Internal.Unsigned.maxBound# not evaluated at compile-time #155
      • CLaSH.Sized.Internal.Unsigned.minBound# not evaluated at compile-time #157
      • Values of type Index 'n', where 'n' > 2MACHINE_WIDTH, incorrectly considered non-synthesisable due to overflow
      • VHDL: Types in generated types.vhdl incorrectly sorted
      • Casts of CLaSH numeric types result in incorrect VHDL/Verilog (Such casts are now reported as an error)
  • v0.6.19 Changes

    June 09, 2016
    • 🛠 Fixes bugs:
      • Eq instance of Vec sometimes not synthesisable
      • VHDL: Converting product types to std_logic_vector fails when the clash-hdlsyn Vivado flag is enabled