All Versions
37
Latest Version
Avg Release Cycle
45 days
Latest Release
2536 days ago

Changelog History
Page 3

  • v0.9.1 Changes

    June 26, 2015
    • 📚 Updated documentation on data-file support on Altera/Quartus

  • v0.9 Changes

    June 25, 2015
    • 🆕 New features:
      • Add operations on singleton natural numbers: addSNat, subSNat, mulSNat, and powSNat.
      • Add asynchronous RAM functions in CLaSH.Prelude.RAM, which have an asynchronous/combinational read port.
      • Add ROM functions in modules CLaSH.Prelude.ROM and CLaSH.Prelude.ROM.File, where the latter module contains functions that instantiate a ROM from the content specified in an external data-file.
      • Add BlockRam functions, in the CLaSH.Prelude.BlockRam.File module, whose content can be initialised with the content specified in an external data-file.
      • assert now takes an extra String argument so you can distinguish one assert from the others. Additionally, assert' is added which takes an additional SClock argument. This is needed, because assert now reports the clock cycle, and clock domain, when an assertion fails.
      • defClkAltera and defClkXilinx are replaced by, altpll and alteraPll for Altera clock sources, and clockWizard for Xilinx clock sources. These names correspond to the names of the generator utilities in Quartus and ISE/Vivado.
      • Add Safe versions of the prelude modules: CLaSH.Prelude.Safe and CLaSH.Prelude.Explicit.Safe
      • Add synchronizers in the CLaSH.Prelude.Synchronizer module

  • v0.8 Changes

    June 03, 2015

    • 🆕 New features:

      • Make the (Bit)Vector argument the last argument for the following functions: slice, setSlice, replaceBit, replace. The signatures for the above functions are now:
      slice      :: BitPack a => SNat m -> SNat n -> a -> BitVector (m + 1 - n)
setSlice   :: BitPack a => SNat m -> SNat n -> BitVector (m + 1 - n) -> a -> a
replaceBit :: Integral i => i -> Bit -> a -> a
replace    :: Integral i => i -> a -> Vec n a -> Vec n a

      This allows for easier chaining, e.g.:

      replaceBit 0 1 $
repleceBit 4 0 $
replaceBit 6 1 bv
      • Until version 0.7.5, given x :: Vec 8 Bit and y :: BitVector 8, it used to be last x == msb y. This is quite confusing when printing converted values. Until version 0.7.5 we would get:
      > 0x0F :: BitVector 8
0000_1111
> unpack 0x0F :: Vec 8 Bit
<1,1,1,1,0,0,0,0>

      As of version 0.8, we have head x == msb y:

      > 0x0F :: BitVector 8
0000_1111
> unpack 0x0F :: Vec 8 Bit
<0,0,0,0,1,1,1,1>

      So converting for Vectors of Bits to BitVectors is no longer index-preserving, but it is order-preserving.

      • Add QuickCheck Arbitary and CoArbitary instances for all data types
      • Add lens Ixed instances for BitVector, Signed, Unsigned, and Vec

  • v0.7.5 Changes

    May 07, 2015
    • 🆕 New features:
      • Moore machine combinators

  • v0.7.4 Changes

    May 05, 2015
    • 🆕 New features:
      • Add TopEntity annotations

  • v0.7.3 Changes

    April 22, 2015

  • v0.7.2 Changes

    April 20, 2015

  • v0.7.1 Changes

    March 25, 2015
    • 🛠 Fixes bugs:
      • Fix laziness bug in Vector.(!!) and Vector.replace

  • v0.7 Changes

    March 13, 2015

    • 🆕 New features:

      • Switch types of bundle and bundle', and unbundle and unbundle'.
      • Rename all explicitly clocked versions of Signal functions, to the primed name of the implicitly clocked Signal functions. E.g. cregister is now called register' (where the implicitly clocked function is callled register)
      • Add new instances for DSignal
      • Add experimental antiDelay function for DSignal
      • Generalize lifted functions over Signals (e.g. (.==.))

    • 🛠 Fixes bugs:

      • Faster versions of Vector.(!!) and Vector.replace

  • v0.6 Changes

    November 17, 2014

    • 🆕 New features:

      • Add Fractional instance for Fixed #9
      • Make indexing/subscript of Vec ascending #4
      • Add separate BitVector type, which has a descending index.
      • Add bit indexing operators, including the index/subscript operator (!).
      • Add bit reduction operators: reduceOr, reduceAnd, reduceOr.
      • Rename BitVector class to BitPack with pack and unpack class methods.
      • Rename Pack class to Bundle with bundle and unbundle class methods.
      • Strip all Vec functions from their v prefix, i.e. vmap -> map.
      • Rename Vec indexing operator from (!) to (!!).
      • Combine Add and Mult class into ExtendingNum class.
      • Add extend and truncate methods to the Resize class.
      • Add SaturatingNum class with saturating numeric operators.
      • Add multitude of lifted Signal operators, i.e. (.==.) :: Eq a => Signal a -> Signal a -> Signal Bool
      • Add CLaSH.Signal.Delayed with functions and data types for delay-annotated signals to support safe synchronisation.
      • Add CLASH.Prelude.DataFlow with functions and data types to create self-synchronising circuits based on data-flow principles.

    • 🛠 Fixes bugs:

      • Remove deprecated 'Arrow' instance for and related functions for Comp #5